library ieee;
use ieee.std_logic_1164.all;
use work.pack.all;

entity cell is
  port (col            : in  integer range 0 to 127;
        line           : in  integer range 0 to 95;
        tela           : in  matriz;
        cor, pixel_bit : out std_logic);
end cell;

architecture bhv of cell is

begin
  process(all) is
  begin
    if col > 31 and col < 96 and line > 23 and line < 72 then
      if tela(col-32)(line-24) = '1' then
        pixel_bit <= '1';
        cor       <= '1';
      else
        pixel_bit <= '0';
        cor       <= '1';
      end if;
    else
      pixel_bit <= '1';
      cor       <= '0';
    end if;
  end process;
end bhv;
